1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an H bridge circuit.
2. Description of Related Art
H bridge circuits formed of power transistors are mainly used for drive control of motors, and in recent years, embedded in semiconductor devices for use.
FIG. 10 shows an H bridge circuit 100 generally having a two-channel structure as a related art. The H bridge circuit 100 includes P type power MOS transistors Qp1, Qp2, Qp3, and Qp4, N type power MOS transistors Qn1, Qn2, Qn3, and Qn4, and loads 131 and 132 such as motors. Each of the P type power MOS transistors Qp1 to Qp4 and each of the N type power MOS transistors Qn1 to Qn4 form a pair, respectively, and each pair is connected in series between VM pads 111 supplying a power supply voltage VM and GND pads 112 supplying a ground voltage GND. The loads 131 and 132 are connected between output pads 113. Each of the transistors Qp1 to Qp4, Qn1 to Qn4 and each of the pads 111, 112, and 113 are electrically connected by aluminum wirings formed in layers. A technique of forming the aluminum wiring layer by two layers for the purpose of reducing a layout area is disclosed in Japanese Unexamined Patent Application Publication No. 2000-311953 (patent document 1).
FIGS. 11 to 13 show examples in which the structure of patent document 1 (one-channel structure) is arranged into the two-channel structure. First, as shown in FIG. 11, a layout of a semiconductor chip 101 includes nine pads including three GND pads 112, two VM pads 111, and four output pads 113, cells 121 forming N type power MOS transistors Qn1, Qn2, Qn3, and Qn4, and cells 122 forming P type power MOS transistors Qp1, Qp2, Qp3, and Qp4. In the drawings, the GND pad 112 is indicated by “G”, the VM pad by “V”, and the output pad by “O”.
In the cells 121 and 122, there are formed source regions 131, drain regions 132, and gate electrodes 133. When a power transistor is formed on the semiconductor substrate in general, a source region, a gate electrode, a drain region, a gate electrode, a source region, . . . are repeatedly arranged in this order. While the source region 131 and the drain region 132 are diffusion layers formed in the semiconductor substrate, the gate electrode 133 is a polysilicon wiring formed on the semiconductor substrate through a gate oxide film or the like (not shown). Note that the gate electrodes 133 are commonly connected and electrically connected to a gate pad or the like (not shown).
The pads 111, 112, and 113 are arranged in a line of G, O, V, O, G, O, V, O, G in this order along with a chip end 29a in a X direction in FIG. 11. Further, the P type power MOS transistors Qp1 to Qp4 and the N type power MOS transistors Qn1 to Qn4 are arranged in a line of Qn1, Qp1, Qp2, Qn2, Qn3, Qp3, Qp4, and Qn4 in this order inside the chip of the pads 111, 112, and 113 in a X direction in FIG. 11.
Next, a wiring structure of the semiconductor chip 101 will be described with reference to FIGS. 12 and 13. FIG. 12 is an upper diagram showing an aluminum wiring layer in a lower layer. Note that the source region 131 and the drain region 132 shown in FIG. 11 are omitted. A source wiring 141 and a drain wiring 142 are formed as aluminum wirings in the upper part of the source region 131 and the drain region 132 with an interlayer insulating film interposed therebetween. Each of the source region 131 and the source wiring 141, and the drain region 132 and the drain wiring 142 is electrically connected by a contact (not shown) penetrating the interlayer insulating film.
FIG. 13 is an upper diagram showing the aluminum wiring layer of the upper layer. As shown in FIG. 13, a source leading-out line 151 electrically connected to the VM pad 111, a source leading-out line 152 electrically connected to the GND pad 112, and a drain leading-out line 153 electrically connected to the output pad 113 are formed in the upper part of the drain wiring 142 and the source wiring 141 that are aluminum wiring layers of the lower layer with the interlayer insulating film interposed therebetween. Each of the source leading-out lines 151 and 152 is connected to the underlying source wiring 141 of FIG. 12 by a contact 154 penetrating the interlayer insulating film. Similarly, the drain leading-out line 153 is electrically connected to the underlying drain wiring 142 of FIG. 12 by a contact 155 penetrating the interlayer insulating film. The source leading-out lines 151, 152 and the drain leading-out line 153 are formed of wiring layers having large width so as to cover substantially half of each cell which is the area where the transistor is formed in order to increase the cross-sectional area of the wiring.